Z8F1680SH020SG Datasheet, PDF (273/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
248
Bit
[3]
TXI
[2]
NAK
[1]
FLUSH
[0]
FILTEN
Description (Continued)
Enable TDRE Interrupts
This bit enables interrupts when the I²C Data Register is empty.
Send NAK
Setting this bit sends a Not Acknowledge condition after the next byte of data has been
received. It is automatically deasserted after the Not Acknowledge is sent or the IEN bit is
cleared. If this bit is 1, it cannot be cleared to 0 by writing to the register.
Flush Data
Setting this bit clears the I²C Data Register and sets the TDRE bit to 1. This bit allows flushing
of the I²C Data Register when an NAK condition is received after the next data byte is written
to the I²C Data Register. Reading this bit always returns 0.
I²C Signal Filter Enable
Setting this bit enables low-pass digital filters on the SDA and SCL input signals. This function
provides the spike suppression filter required in I²C Fast Mode. These filters reject any input
pulse with periods less than a full system clock cycle. The filters introduce a 3-system clock
cycle latency on the inputs.
17.3.4. I²C Baud Rate High and Low Byte Registers
The I²C Baud Rate High and Low Byte registers, shown in Tables 122 and 123, combine
to form a 16-bit reload value, BRG[15:0], for the I²C Baud Rate Generator. The I²C baud
rate is calculated using the following equation.
I²C Baud Rate (bits/s) = ^{System Clock Frequency (Hz)}
4 x BRG[15:0]
Note: If BRG = 0000H, use 10000H in the equation.
Table 122. I²C Baud Rate High Byte Register (I2CBRH = 53H)
Bits
7
6
5
4
3
2
1
0
Field
BRH
Reset
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
F53H
Bit Position
[7:0]
BRH
Value
Description
I²C Baud Rate High Byte
The most significant byte, BRG[15:8], of the I²C Baud Rate Generator’s reload value.
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller