Z8F1680SH020SG Datasheet, PDF (260/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
235
1. The software initializes the MODE field in the I²C Mode Register for MASTER/
SLAVE Mode with 7- or 10-bit addressing (the I²C bus protocol allows the mixing of
slave address types). The MODE field selects the address width for this mode when
addressed as a slave (but not for the remote slave). The software asserts the IEN bit in
the I²C Control Register.
2. The software writes 11110b, followed by the two most-significant address bits and a
0 (write) to the I²C Data Register.
3. The software asserts the start bit of the I²C Control Register.
4. The I²C controller sends a start condition.
5. The I²C controller loads the I²C Shift Register with the contents of the I²C Data
Register.
6. After the first bit has been shifted out, a transmit interrupt is asserted.
7. The software responds by writing the least significant eight bits of address to the I²C
Data Register.
8. The I²C controller completes shifting of the first address byte.
9. The I²C slave sends an Acknowledge by pulling the SDA signal Low during the next
High period of SCL.
If the slave does not acknowledge the address byte, the I²C controller sets the NCKI
bit in the I²C Status Register, sets the ACKV bit and clears the ACK bit in the I²C
State Register. The software responds to the Not Acknowledge interrupt by setting the
stop bit and clearing the TXI bit. The I²C controller flushes the Transmit Data
Register, sends the stop condition on the bus and clears the stop and NCKI bits. The
transaction is complete and the following steps can be ignored.
10. The I²C controller loads the I²C Shift Register with the contents of the I²C Data
Register (the lower byte of the 10-bit address).
11. The I²C controller shifts out the next eight bits of the address. After the first bit shifts,
the I²C controller generates a transmit interrupt.
12. The software responds by setting the start bit of the I²C Control Register to generate a
repeated start condition.
13. The software writes 11110b, followed by the 2-bit slave address and a 1 (Read) to the
I²C Data Register.
14. If the user chooses to read only one byte, the software responds by setting the NAK bit
of the I²C Control Register.
15. After the I²C controller shifts out the address bits listed in Step 9 (the second address
transfer), the I²C slave sends an Acknowledge by pulling the SDA signal Low during
the next High period of SCL.
If the slave does not acknowledge the address byte, the I²C controller sets the NCKI
bit in the I²C Status Register, sets the ACKV bit and clears the ACK bit in the I²C
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller