Z8F1680SH020SG Datasheet, PDF (140/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
115
Bit
[6] (cont’d)
Description (Continued)
PWM DUAL OUTPUT Mode
0 = Timer Output is forced Low (0) and Timer Output Complement is forced High (1) when
the timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM
count match and forced Low (0) upon Reload. When enabled, the Timer Output
Complement is forced Low (0) upon PWM count match and forced High (1) upon
Reload. The PWMD field in Timer Control 0 Register is a programmable delay to control
the number of cycles time delay before the Timer Output and the Timer Output
Complement is forced to High (1).
1 = Timer Output is forced High (1) and Timer Output Complement is forced Low (0) when
the timer is disabled. When enabled, the Timer Output is forced Low (0) upon PWM
count match and forced High (1) upon Reload. When enabled, the Timer Output
Complement is forced High (1) upon PWM count match and forced Low (0) upon
Reload. The PWMD field in Timer Control 0 Register is a programmable delay to control
the number of cycles time delay before the Timer Output and the Timer Output
Complement is forced to Low (0).
CAPTURE RESTART Mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
COMPARATOR COUNTER Mode
When the timer is disabled, the Timer Output signal is set to the value of this bit. When the
timer is enabled, the Timer Output signal is complemented upon timer reload.
TRIGGERED ONE-SHOT Mode
0 = Timer counting is triggered on the rising edge of the Timer Input signal.
1 = Timer counting is triggered on the falling edge of the Timer Input signal.
DEMODULATION Mode
0 = Timer counting is triggered on the rising edge of the Timer Input signal. The current
count is captured into PWM0 High and Low byte registers on subsequent rising edges of
the Timer Input signal.
1 = Timer counting is triggered on the falling edge of the Timer Input signal. The current
count is captured into PWM1 High and Low byte registers on subsequent falling edges
of the Timer Input signal.
The above functionality applies only if TPOLHI bit in Timer Control 2 Register is 0. If
TPOLHI bit is 1 then timer counting is triggered on any edge of the Timer Input signal and
the current count is captured on both edges. The current count is captured into PWM0
registers on rising edges and PWM1 registers on falling edges of the Timer Input signal.
PS025015-1212
PRELIMINARY
Timers