Z8F1680SH020SG Datasheet, PDF (110/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
85
9.1.
Architecture
Figure 11 displays the architecture of the timers.
Data
Bus
Block
Control
Peripheral
Clock
System
Clock
Timer
Input
Timer
Control
Timer Block
16-bit
Reload Register
16-bit Counter
with Prescaler
Interrupt,
PWM,
and
Timer Output
Control
Gate
Input
Capture
Input
Two 16-bit
PWM/Compare
Figure 11. Timer Block Diagram
Timer
Interrupt
TOUT
TOUT
9.2.
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value
0001H into the Timer Reload High and Low Byte registers and setting the prescale value
to 1. Maximum time-out delay is set by loading the value 0000H into the Timer Reload
High and Low Byte registers and setting the prescale value to 128. If the Timer reaches
FFFFH, the timer rolls over to 0000H and continues counting.
9.2.1. Timer Clock Source
The timer clock source can come from either the peripheral clock or the system clock.
Peripheral clock is based on a low frequency/low power 32 kHz secondary oscillator that
can be used with external watch crystal. Peripheral clock source is only available for
driving Timer and Noise Filter operation. It is not supported for other peripherals.
For timer operation in STOP Mode, peripheral clock must be selected as the clock source.
Peripheral clock can be selected as source for both ACTIVE and STOP Mode operation.
PS025015-1212
PRELIMINARY
Timers