Z8F1680SH020SG Datasheet, PDF (178/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
153
interrupts to go inactive until the next address byte. If the new frame’s address matches the
LIN-UART’s, then the data in the new frame is also processed.
The second scheme is enabled by setting MPMD[1:0] to 10B and writing the LIN-UART’s
address into the LIN-UART Address Compare Register. This mode introduces more
hardware control, interrupting only on frames that match the LIN-UART’s address. When
an incoming address byte does not match the LIN-UART’s address, it is ignored. All
successive data bytes in this frame are also ignored. When a matching address byte occurs,
an interrupt is issued and further interrupts occur on each successive data byte. The first
data byte in the frame has NEWFRM=1 in the LIN-UART Status 1 Register. When the
next address byte occurs, the hardware compares it to the LIN-UART’s address. If there is
a match, the interrupt occurs and the NEWFRM bit is set to the first byte of the new frame.
If there is no match, the LIN-UART ignores all incoming bytes until the next address
match.
The third scheme is enabled by setting MPMD[1:0] to 11B and by writing the LIN-
UART’s address into the LIN-UART Address Compare Register. This mode is identical to
the second scheme, except that there are no interrupts on address bytes. The first data byte
of each frame remains accompanied by a NEWFRM assertion.
12.1.10. LIN Protocol Mode
The Local Interconnect Network (LIN) protocol as supported by the LIN-UART module is
defined in rev 2.0 of the LIN Specification Package. The LIN protocol specification
covers all aspects of transferring information between LIN Master and Slave devices using
message frames including error detection and recovery, SLEEP Mode and wake-up from
SLEEP Mode. The LIN-UART hardware in LIN mode provides character transfers to
support the LIN protocol including break transmission and detection, wake-up
transmission and detection and slave autobauding. Part of the error detection of the LIN
protocol is for both master and slave devices to monitor their receive data when
transmitting. If the receive and transmit data streams do not match, the LIN-UART asserts
the PLE bit (physical layer error bit in Status 0 Register). The message frame time-out
aspect of the protocol depends on software requiring the use of an additional general
purpose timer. The LIN mode of the LIN-UART does not provide any hardware support
for computing/verifying the checksum field or verifying the contents of the identifier field.
These fields are treated as data and are not interpreted by hardware. The checksum
calculation/verification can easily be implemented in software via the ADC (Add with
Carry) instruction.
The LIN bus contains a single Master and one or more Slaves. The LIN master is
responsible for transmitting the message frame header which consists of the Break, Synch
and Identifier fields. Either the master or one of the slaves transmits the associated
response section of the message which consists of data characters followed by a checksum
character.
PS025015-1212
PRELIMINARY
LIN-UART