Z8F1680SH020SG Datasheet, PDF (142/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
117
9.3.5.3. Timer 0–2 Control 2 Register
The Timer 0–2 Control 2 (TxCTL2) registers allow selection of timer clock source and
control of timer input polarity in DEMODULATION Mode. See Table 65.
Table 65. Timer 0–2 Control 2 Register (TxCTL2)
Bit
Field
Reset
R/W
Address
7
6
5
4
3
2
1
Reserved
PWM0UE TPOLHI
Reserved
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F22H, F26H, F2AH
0
TCLKS*
0
R/W
Bit
Description
[7:6]
Reserved; must be 0.
[5]
PWM0 Update Enable
PWM0UE This bit determines whether writes to the PWM0 High and Low Byte registers are buffered
when TEN = 1. Writes to these registers are not buffered when TEN = 0, regardless of the
value of this bit.
0 = Writes to the Channel High and Low Byte registers are buffered when TEN = 1 and only
take affect on a timer reload to 0001H.
1 = Writes to the Channel High and Low Byte registers are not buffered when TEN = 1.
[4]
TPOLHI
Timer Input/Output Polarity High Bit
This bit determines if timer count is triggered and captured on both edges of the input signal.
This applies only to DEMODULATION Mode.
0 = Count is captured only on one edge in DEMODULATION Mode. In this case, edge polarity
is determined by TPOL bit in the TxCTL1 Register.
1 = Count is triggered on any edge and captured on both rising and falling edges of the Timer
Input signal in DEMODULATION Mode.
[3:1]
Reserved; must be 0.
[0]
TCLKS
Timer Clock Source
0 = System Clock.
1 = Peripheral Clock.*
Note: *Before selecting the peripheral clock as the timer clock source, the peripheral clock must be enabled and os-
cillating.
PS025015-1212
PRELIMINARY
Timers