Z8F1680SH020SG Datasheet, PDF (244/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
219
16.4.5. ESPI Status Register
The ESPI Status Register, shown in Table 113, indicates the current state of the ESPI. All
bits revert to their Reset state if the ESPI is disabled.
Table 113. ESPI Status Register (ESPISTAT)
Bits
7
6
5
4
3
Field
TDRE TUND
COL
ABT
ROVR
Reset
1
0
0
0
0
R/W
R
R/W*
R/W*
R/W*
R/W*
Address
F64H
Note: R/W* = Read access. Write a 1 to clear the bit to 0.
2
RDRNE
0
R
1
TFST
0
R
0
SLAS
1
R
Bit
[7]
TDRE
[6]
TUND
[5]
COL
[4]
ABT
[3]
ROVR
[2]
RDRNE
Description
Transmit Data Register Empty
0 = Transmit Data Register is full or ESPI is disabled.
1 = Transmit Data Register is empty. A write to the ESPI (Transmit) Data Register clears this bit.
Transmit Underrun
0 = A Transmit Underrun error has not occurred.
1 = A Transmit Underrun error has occurred.
Collision
0 = A multi-Master collision (mode fault) has not occurred.
1 = A multi-Master collision (mode fault) has occurred.
SLAVE Mode Transaction Abort
This bit is set if the ESPI is configured in SLAVE Mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS field
of the ESPIMODE register. This bit can also be set in SLAVE Mode by an SCK monitor time-
out (MMEN = 0, BRGCTL = 1).
0 = A SLAVE Mode transaction abort has not occurred.
1 = A SLAVE Mode transaction abort has occurred.
Receive Overrun
0 = A Receive Overrun error has not occurred.
1 = A Receive Overrun error has occurred.
Receive Data Register Not Empty
0 = Receive Data Register is empty.
1 = Receive Data Register is not empty.
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface