Z8F1680SH020SG Datasheet, PDF (120/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
95
PWM Period (s)
=
------R----e---l-o---a---d----V-----a--l--u---e----^-----P---r--e---s--c---a---l-e-------
Timer Clock Frequency (Hz)
If TPOL is set to 0, the ratio of the PWM output High time to the total period is calculated
using the following equation:
PWM Output High Time Ratio (%)
=
R----e---l--o---a---d----V----a---l--u---e--------P----W-----M-------V-----a--l--u---e-
Reload Value

100
If TPOL is set to 1, the ratio of the PWM output High time to the total period is calculated
using the following equation:
PWM Output High Time Ratio (%) = --P---W------M-------V----a---l-u---e---  100
Reload Value
9.2.3.7. PWM DUAL Output Mode
In PWM DUAL OUTPUT Mode, the timer outputs a Pulse Width Modulator output signal
and also its complement through two GPIO port pins. The timer first counts up to the 16-
bit PWM match value stored in the Timer PWM0 High and Low Byte registers. When the
timer count value matches the PWM value, the Timer Outputs (TOUT and TOUT) toggle.
The timer continues counting until it reaches the reload value stored in the Timer Reload
High and Low Byte registers. Upon reaching the reload value, the timer generates an inter-
rupt, the count value in the Timer High and Low Byte registers is reset to 0001H and
TOUT and TOUT toggles again and counting resumes.
If the TPOL bit in the Timer Control 1 Register is set to 1, the Timer Output signal begins
as High (1) and then transitions to Low (0) when the timer value matches the PWM value.
The Timer Output signal returns to High (1) after the timer reaches the reload value and is
reset to 0001H.
If the TPOL bit in the Timer Control 1 Register is set to 0, the Timer Output signal begins
as Low (0) and then transitions to High (1) when the timer value matches the PWM value.
The Timer Output signal returns to Low (0) after the timer reaches the reload value and is
reset to 0001H.
The timer also generates a second PWM output signal, Timer Output Complement
(TOUT). TOUT is the complement of the Timer Output PWM signal (TOUT). A
programmable deadband delay can be configured to set a time delay (0 to 128 timer clock
cycles) when one PWM output transitions from High to Low and the other PWM output
PS025015-1212
PRELIMINARY
Timers