Z8F1680SH020SG Datasheet, PDF (248/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
223
Chapter 17. I²C Master/Slave Controller
The I²C Master/Slave Controller ensures that the Z8 Encore! XP F1680 Series devices are
bus-compatible with the I²C protocol. The I²C bus consists of the serial data signal (SDA)
and a serial clock signal (SCL) bidirectional lines. The features of I²C controller include:
• Operates in MASTER/SLAVE or SLAVE ONLY modes
• Supports arbitration in a multimaster environment (MASTER/SLAVE Mode)
• Supports data rates up to 400 Kbps
• 7-bit or 10-bit slave address recognition (interrupt only on address match)
• Optional general call address recognition
• Optional digital filter on receive SDA, SCL lines
• Optional interactive receive mode allows software interpretation of each received ad-
dress and/or data byte before acknowledging
• Unrestricted number of data bytes per transfer
• Baud Rate Generator can be used as a general-purpose timer with an interrupt, if the
I²C controller is disabled
17.1. Architecture
Figure 42 displays the architecture of the I²C controller.
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller