Z8F1680SH020SG Datasheet, PDF (153/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
128
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0H
t0
t1
t0
t0
t1
t0
t1
Figure 18. Count Max Mode with Channel Compare
10.7. Multi-Channel Timer Control Register Definitions
This section defines the features of the following Multi-Channel Timer Control registers.
Multi-Channel Timer High and Low Byte Registers: see page 130
Multi-Channel Timer Reload High and Low Byte Registers: see page 130
Multi-Channel Timer Subaddress Register: see page 131
Multi-Channel Timer Subregister x (0, 1, or 2): see page 132
Multi-Channel Timer Control 0, Control 1 Registers: see page 132
Multi-Channel Timer Channel Status 0 and Status 1 Registers: see page 135
Multi-Channel Timer Channel-y Control Registers: see page 137
Multi-Channel Timer Channel-y High and Low Byte Registers: see page 139
10.7.1. Multi-Channel Timer Address Map
Table 69 defines the byte address offsets for the Multi-channel Timer registers. For saving
address space, a subaddress is used for the Timer Control 0, Timer Control 1, Channel
Status 0, Channel Status 1, Channel-y Control, and Channel-y High and Low byte
registers. Only the Timer High and Low Byte registers and the Reload High and Low Byte
registers can be directly accessed.
PS025015-1212
PRELIMINARY
Multi-Channel Timer