Z8F1680SH020SG Datasheet, PDF (108/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
83
Bit
[5]
PA5CS
[4:1]
PADxS
[0]
Description
PA5/Comparator 1 Selection
0 = PA5 is used for the interrupt for PA5CS interrupt request.
1 = The Comparator 1 is used for the interrupt for PA5CS interrupt request.
PAx/PDx Selection
0 = PAx is used for the interrupt for PAx/PDx interrupt request
1 = PDx is used for the interrupt for PAx/PDx interrupt request; an x indicates the specific
GPIO port pin number (1–4).
Reserved; must be 0.
8.4.9. Interrupt Control Register
Bits
Field
Reset
R/W
Address
The Interrupt Control (IRQCTL) Register, shown in Table 51, contains the master enable
bit for all interrupts.
Table 51. Interrupt Control Register (IRQCTL)
7
6
5
4
3
2
1
0
IRQE
Reserved
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
FCFH
Bit
[7]
IRQE
[6:0]
Description
Interrupt Request Enable
This bit is set to 1 by executing an Enable Interrupts (EI) or IRET (Interrupt Return) instruction,
or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI instruction, eZ8
CPU acknowledgement of an interrupt request, a Reset, or by a direct register write of a 0 to
this bit.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
Reserved; must be 0.
PS025015-1212
PRELIMINARY
Interrupt Controller