Z8F1680SH020SG Datasheet, PDF (226/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
201
16.3.1. Throughput
In MASTER Mode, the maximum SCK rate supported is one-half the system clock
frequency. This rate is achieved by programming the value 0001H into the Baud Rate
High/Low register pair. Though each character will be transferred at this rate it is unlikely
that software interrupt routines could keep up with this rate. In SPI mode the transfer will
automatically pause between characters until the current receive character is read and the
next transmit data value is written.
In SLAVE Mode, the transfer rate is controlled by the Master. As long as the TDRE and
RDRNE interrupt are serviced before the next character transfer completes, the Slave will
keep up with the Master. In SLAVE Mode the baud rate must be restricted to a maximum
of one-eighth of the system clock frequency to allow for synchronization of the SCK input
to the internal system clock.
16.3.2. ESPI Clock Phase and Polarity Control
The ESPI supports four combinations of serial clock phase and polarity using two bits in
the ESPI Control Register. The clock polarity bit, CLKPOL, selects an active High or
active Low clock and has no effect on the transfer format. Table 108 lists the ESPI Clock
Phase and Polarity Operation parameters. The clock phase bit, PHASE, selects one of two
fundamentally different transfer formats. The data is output a half-cycle before the receive
clock edge which provides a half cycle of setup and hold time.
Table 108. ESPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation
PHASE
0
0
1
1
CLKPOL
0
1
0
1
SCK Transmit Edge
Falling
Rising
Rising
Falling
SCK Receive Edge
Rising
Falling
Falling
Rising
SCK Idle State
Low
High
Low
High
16.3.2.1. Transfer Format when Phase Equals Zero
Figure 34 displays the timing diagram for an SPI type transfer, in which PHASE = 0. For
SPI transfers the clock only toggles during the character transfer. The two SCK
waveforms show polarity with CLKPOL = 0 and CLKPOL = 1. The diagram can be
interpreted as either a Master or Slave timing diagram because the SCK Master-In/Slave-
Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly connected between the
Master and the Slave.
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface