Z8F1680SH020SG Datasheet, PDF (111/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
86
System clock is only for operation in ACTIVE and HALT modes. System clock is
software selectable in Oscillator Control Module as external high-frequency crystal or
internal precision oscillator. The TCLKS field in the Timer Control 2 Register selects the
timer clock source.
Caution: When the timer is operating on a peripheral clock, the timer clock is asynchronous to
the CPU clock. To ensure error-free operation, disable the timer before modifying its op-
eration (also include changing the timer clock source). Therefore, any write to the timer
control registers cannot be performed when the timer is enabled and a peripheral clock
is used.
When the timer uses a peripheral clock and the timer is enabled, any read from TxH or
TxL is not recommended, because the results can be unpredictable. Disable the timer first,
then read it. If the timer works in the CAPTURE, CAPTURE/COMPARE, CAPTURE
RESTART or DEMODULATION modes, any read from TxPWM0H, TxPWM0L,
TxPWM1H, TxPWM1L or TxSTAT must be performed after a capture interrupt occurs;
otherwise, results can be unpredictable. The INPCAP bit of the Timer Control 0 Register
is the same as these PWM registers. When the timer uses the main clock, you can write/
read all timer registers at any time.
9.2.2. Low-Power Modes
Timers can operate in both HALT Mode and STOP Mode.
9.2.2.1. Operation in HALT Mode
When the eZ8 CPU enters HALT Mode, the timer will continue to operate if enabled. To
minimize current in HALT Mode, the timer can be disabled by clearing the TEN control
bit. The noise filter, if enabled, will also continue to operate in HALT Mode and rejects
any noise on the timer input pin.
9.2.2.2. Operation in STOP Mode
When the eZ8 CPU enters STOP Mode, the timer continues to operate if enabled and
peripheral clock is chosen as the clock source. In STOP Mode, the timer interrupt (if
enabled) automatically initiates a Stop Mode Recovery and generates an interrupt request.
In the Reset Status Register, the stop bit is set to 1. Also, timer interrupt request bit in
Interrupt Request 0 register is set. Following completion of the Stop Mode Recovery, if
interrupts are enabled, the CPU responds to the interrupt request by fetching the timer
interrupt vector. The noise filter, if enabled, will also continue to operate in STOP Mode
and rejects any noise on the timer input pin.
PS025015-1212
PRELIMINARY
Timers