Z8F1680SH020SG Datasheet, PDF (394/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
369
29.4.4. UART Timing
Figure 78 and Table 207 provide timing information for the UART pins for situations in
which CTS is used for flow control. The CTS to DE assertion delay (T1) assumes that the
Transmit Data Register has been loaded with data prior to CTS assertion.
CTS
(Input)
DE
(Output)
T₃
T₁
TXD
(Output)
bit 7 parity stop
end of
stop bit(s)
start bit 0
bit 1
T₂
Figure 78. UART Timing With CTS
Table 207. UART Timing with CTS
Parameter Abbreviation
UART
T₁
CTS Fall to DE output delay
T₂
DE assertion to TXD falling edge (start bit) delay
T₃
End of stop bit(s) to DE deassertion delay
Delay (ns)
Min
Max
2 * X_IN period
±5
±5
2 * X_IN period
+ 1 bit time
Figure 79 and Table 208 provide timing information for the UART pins for situations in
which CTS is not used for flow control. DE asserts after the Transmit Data Register has
been written. DE remains asserted for multiple characters as long as the Transmit Data
Register is written with the next character before the current character has completed.
PS025015-1212
PRELIMINARY
Electrical Characteristics