Z8F1680SH020SG Datasheet, PDF (272/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
247
17.3.3. I²C Control Register
The I²C Control Register, shown in Table 121, enables and configures I²C operation.
Note: The R/W1 bit can be set (written to 1) when IEN = 1, but cannot be cleared (written to 0).
Bits
7
Field
IEN
Reset
0
R/W
R/W
Address
Table 121. I²C Control Register (I2CCTL)
6
START
0
R/W1
5
STOP
0
R/W1
4
3
BIRQ
TXI
0
0
R/W
R/W
F52H
2
NAK
0
R/W1
1
FLUSH
0
W
0
FILTEN
0
R/W
Bit
[7]
IEN
[6]
START
[5]
STOP
[4]
BIRQ
Description
I²C Enable
This bit enables the I²C controller.
Send Start Condition
When set, this bit causes the I²C controller (when configured as the master) to send a start
condition. After it is asserted, this bit is cleared by the I²C controller after it sends the start
condition or by deasserting the IEN bit. If this bit is 1, it cannot be cleared by writing to the bit.
After this bit is set, a start condition is sent if there is data in the I2CDATA or I²C Shift Register.
If there is no data in one of these registers, the I²C controller waits until data is loaded. If this
bit is set while the I²C controller is shifting out data, it generates a restart condition after the
byte shifts and the Acknowledge phase completes. If the stop bit is also set, it waits until the
stop condition is sent before the start condition. If start is set while a SLAVE Mode transaction
is underway to this device, the start bit will be cleared and ARBLST bit in the Interrupt Status
Register will be set.
Send Stop Condition
When set, this bit causes the I²C controller (when configured as the master) to send the stop
condition after the byte in the I²C Shift Register has completed transmission or after a byte is
received in a receive operation. When set, this bit is reset by the I²C controller after a stop
condition has been sent or by deasserting the IEN bit. If this bit is 1, it cannot be cleared to 0 by
writing to the register. If stop is set while a SLAVE Mode transaction is underway, the stop bit is
cleared by hardware.
Baud Rate Generator Interrupt Request
This bit is ignored when the I²C controller is enabled. If this bit is set = 1 when the I²C controller
is disabled (IEN = 0), the baud rate generator is used as an additional timer causing an
interrupt to occur every time the baud rate generator counts down to one. The baud rate
generator runs continuously in this mode, generating periodic interrupts.
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller