Z8F1680SH020SG Datasheet, PDF (50/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
25
Table 8. Register File Address Map (Continued)
Address (Hex) Register Description
F17
Timer 2 Control 1
F28
Timer 2 PWM1 High Byte
F29
Timer 2 PWM1 Low Byte
F2A
Timer 2 Control 2
F2B
Timer 2 Status
F2E
Timer 2 Noise Filter Control
F2F–F3F
Reserved
Mnemonic Reset (Hex)¹ Page #
T2CTL1
00
113
T2PWM1H
00
111
T2PWM1L
00
111
T2CTL2
00
117
T2STA
00
118
T2NFC
00
119
—
XX
LIN UART 0
F40
LIN UART0 Transmit Data
U0TXD
XX
163
LIN UART0 Receive Data
U0RXD
XX
164
F41
LIN UART0 Status 0—Standard UART Mode
U0STAT0 0000011Xb 165
LIN UART0 Status 0—LIN Mode
U0STAT0 00000110b 166
F42
LIN UART0 Control 0
U0CTL0
00
170
F43
LIN UART0 Control 1—Multiprocessor Control U0CTL1
00
172
LIN UART0 Control 1—Noise Filter Control
U0CTL1
00
174
LIN UART0 Control 1—LIN Control
U0CTL1
00
175
F44
LIN UART0 Mode Select and Status
U0MDSTAT
00
168
F45
UART0 Address Compare
U0ADDR
00
177
F46
UART0 Baud Rate High Byte
U0BRH
FF
177
F47
UART0 Baud Rate Low Byte
U0BRL
FF
178
LIN UART 1
F48
LIN UART1 Transmit Data
U1TXD
XX
163
LIN UART1 Receive Data
U1RXD
XX
164
F49
LIN UART1 Status 0—Standard UART Mode
U1STAT0 0000011Xb 165
LIN UART1 Status 0—LIN Mode
U1STAT0 00000110b 166
F4A
LIN UART1 Control 0
U1CTL0
00
170
Notes:
1. XX=Undefined.
2. The Reserved space can be configured as General-Purpose Register File RAM depending on the user option bits
(see the User Option Bits chapter on page 277) and the on-chip PRAM size (see the Ordering Information chapter
on page 372). If the PRAM is programmed as General-Purpose Register File RAM on Reserved space, the start-
ing address always begins immediately after the end of General-Purpose Register File RAM.
PS025015-1212
PRELIMINARY
Register Map