Z8F1680SH020SG Datasheet, PDF (322/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
297
RS232 TX
RS-232
V_DD
Transceiver _Open-Drain
Buffer
10 kΩ
DBG pin
RS232 RX
Figure 58. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, #2 of 2
23.2.1. DEBUG Mode
The operating characteristics of the Z8 Encore! XP F1680 Series device in DEBUG mode
are:
• The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to ex-
ecute specific instructions
• The system clock operates unless in STOP Mode
• All enabled on-chip peripherals operate unless in STOP Mode or otherwise defined by
the on-chip peripheral to disable in DEBUG mode
• Automatically exits HALT Mode
• Constantly refreshes the Watch-Dog Timer, if enabled
23.2.1.1. Entering DEBUG Mode
The device enters DEBUG mode following any of the these operations:
• Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface
• eZ8 CPU execution of a breakpoint (BRK) instruction (when enabled)
• Match of PC to OCDCNTR Register (when enabled)
• OCDCNTR Register decrements to 0000H (when enabled)
• The DBG pin is Low when the device exits Reset
23.2.1.2. Exiting DEBUG Mode
The device exits DEBUG mode following any of these operations:
• Clearing the DBGMODE bit in the OCD Control Register to 0
• Power-on reset
PS025015-1212
PRELIMINARY
On-Chip Debugger