Z8F1680SH020SG Datasheet, PDF (64/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
39
eZ8 CPU services the Timer interrupt request following the normal Stop Mode Recovery
sequence.
5.3.3. Stop Mode Recovery Using Comparator Interrupt
If Comparator enabled for STOP Mode operation interrupts during STOP Mode, the
device undergoes a Stop Mode Recovery sequence. In the Reset Status Register, the stop
bit is set to 1. If the F1680 Series MCU is configured to respond to interrupts, the eZ8
CPU services the comparator interrupt request following the normal Stop Mode Recovery
sequence.
5.3.4. Stop Mode Recovery Using GPIO Port Pin Transition
Each of the GPIO port pins can be configured as a Stop Mode Recovery input source. On
any GPIO pin enabled as a Stop Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop Mode Recovery. In the Reset Sta-
tus Register, the stop bit is set to 1.
Caution: In STOP Mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input
Data registers record the Port transition only if the signal stays on the Port pin until the
end of the Stop Mode Recovery delay. As a result, short pulses on the Port pin can ini-
tiate Stop Mode Recovery without being written to the Port Input Data Register or with-
out initiating an interrupt (if enabled for that pin).
5.3.5. Stop Mode Recovery Using External RESET Pin
When the F1680 Series MCU is in STOP Mode and the external RESET pin is driven
Low, a System Reset occurs. Because of a glitch filter operating on the RESET pin, the
Low pulse must be greater than the minimum width specified, or it is ignored. For details,
see the Electrical Characteristics chapter on page 349.
5.4.
Low-Voltage Detection
In addition to the VBO Reset described earlier, it is also possible to generate an interrupt
when the supply voltage drops below a user-selected value. For more details about the
available Low-Voltage Detection (LVD) threshold levels, see the Trim Option Bits at
Address 0000H (TTEMP0) section on page 282.
When the supply voltage drops below the LVD threshold, the LVD bit of the RSTSTAT
Register is set to 1. This bit remains 1 until the low-voltage condition elapses. Reading or
PS025015-1212
P R E L I M I N A R Y Reset, Stop Mode Recovery and Low-Voltage