Z8F1680SH020SG Datasheet, PDF (138/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
113
Bit
[3:1]
PWMD
[0]
INPCAP
Description (Continued)
PWM Delay Value
This field is a programmable delay to control the number of timer clock cycles time delay
before the Timer Output and the Timer Output Complement is forced to their active state.
000 = No delay
001 = 2 cycles delay
010 = 4 cycles delay
011 = 8 cycles delay
100 = 16 cycles delay
101 = 32 cycles delay
110 = 64 cycles delay
111 = 128 cycles delay
Input Capture Event
This bit indicates if the last timer interrupt is due to a Timer Input Capture Event.
0 = Previous timer interrupt is not a result of Timer Input Capture Event.
1 = Previous timer interrupt is a result of Timer Input Capture Event.
Bit
Field
Reset
R/W
Address
Bit
[7]
TEN
9.3.5.2. Timer 0–2 Control 1 Register
The Timer 0–2 Control 1 (TxCTL1) registers enable and disable the timers, set the pres-
caler value and determine the timer operating mode. See Table 64.
Table 64. Timer 0–2 Control 1 Register (TxCTL1)
7
TEN
0
R/W
6
TPOL
0
R/W
5
4
3
2
1
0
PRES
TMODE
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
F07H, F0FH, F17H
Description
Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
PS025015-1212
PRELIMINARY
Timers