Z8F1680SH020SG Datasheet, PDF (271/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
246
Bit
Description (Continued)
[2]
ARBLST
Arbitration Lost
This bit is set when the I²C controller is enabled in MASTER Mode and loses arbitration
(outputs a 1 on SDA and receives a 0 on SDA). The ARBLST bit clears when the I2CISTAT
Register is read.
[1]
SPRS
Stop/Restart Condition Interrupt
This bit is set when the I²C controller is enabled in SLAVE Mode and detects a stop or restart
condition during a transaction directed to this slave. This bit clears when the I2CISTAT
Register is read. Read the RSTR bit of the I2CSTATE Register to determine whether the
interrupt was caused by a stop or restart condition.
[0]
NCKI
NAK Interrupt
In MASTER Mode, this bit is set when a Not Acknowledge condition is received or sent and
neither the start nor the stop bit is active. In MASTER Mode, this bit can only be cleared by
setting the start or stop bits. In SLAVE Mode, this bit is set when a Not Acknowledge condition
is received (Master reading data from Slave), indicating the master is finished reading. A stop
or restart condition follows. In SLAVE Mode this bit clears when the I2CISTAT Register is read.
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller