Z8F1680SH020SG Datasheet, PDF (228/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
203
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MISO
Input Sample Time
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SS
Figure 35. ESPI Timing when PHASE = 1
16.3.3. Slave Select Modes of Operation
This section describes the different modes of data transfer supported by the ESPI block.
The mode is selected by the Slave Select Mode (SSMD) field of the Mode Register.
16.3.3.1. SPI Mode
This mode is selected by setting the SSMD field of the Mode Register to 00. In this mode
software controls the assertion of the SS signal directly via the SSV bit of the SPI
Transmit Data Command register. Software can be used to control an SPI mode
transaction. Prior to or simultaneously with writing the first transmit data byte; software
sets the SSV bit. Software sets the SSV bit either by performing a byte write to the
Transmit Data Command register prior to writing the first transmit character to the Data
Register or by performing a word write to the Data Register address which loads the first
transmit character and simultaneously sets the SSV bit. SS will remain asserted when one
or more characters are transferred. There are two mechanisms for deasserting SS at the
end of the transaction. One method used by software is to set the TEOF bit of the Transmit
Data Command register, when the last TDRE interrupt is being serviced (set TEOF before
or simultaneously with writing the last data byte). After the last bit of the last character is
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface