Z8F1680SH020SG Datasheet, PDF (182/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
157
rate. To avoid an autobaud overrun error, the system clock must not be greater than 2¹⁹
times the baud rate (16 bit counter following 3-bit prescaler when counting the 8 bit times
of the Autobaud sequence).
Following the Synch character, the LIN-UART hardware transits to the Active state, in
which the identifier character is received and the characters of the response section of the
message are sent or received. The slave remains in this Active state until a break is
received or software forces a state change. After it is in an Active state (i.e., autobaud has
completed), a break of 10 or more bit times is recognized and causes a transition to the
Autobaud state.
If the identifier character indicates that this slave device is not participating in the
message, software sets the LinState[1:0] = 01b (Wait for Break state) to ignore the rest of
the message. No further receive interrupts will occur until the next break.
12.1.11. LIN-UART Interrupts
The LIN-UART features separate interrupts for the transmitter and receiver. In addition,
when the LIN-UART primary functionality is disabled, the Baud Rate Generator can also
function as a basic timer with interrupt capability.
12.1.11.1. Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for
transmission. The TDRE interrupt occurs when the transmitter is initially enabled and
after the Transmit Shift Register has shifted out the first bit of a character. At this point,
the Transmit Data Register can be written with the next character to send. This provides 7
bit periods of latency to load the Transmit Data Register before the Transmit Shift Register
completes shifting the current character. Writing to the LIN-UART Transmit Data Register
clears the TDRE bit to 0.
12.1.11.2. Receiver Interrupts
The receiver generates an interrupt when any one of the following occurs:
• A data byte has been received and is available in the LIN-UART Receive Data Regis-
ter. This interrupt can be disabled independent of the other receiver interrupt sources
via the RDAIRQ bit (this feature is useful in devices which support DMA). The re-
ceived data interrupt occurs after the receive character has been placed in the Receive
Data Register. Software must respond to this received data available condition before
the next character is completely received to avoid an overrun error.
PS025015-1212
PRELIMINARY
LIN-UART