Z8F1680SH020SG Datasheet, PDF (229/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
204
transmitted, the hardware will automatically deassert the SSV and TEOF bits. The second
method is for software to directly clear the SSV bit after the transaction completes. If
software clears the SSV bit directly it is not necessary for software to also set the TEOF bit
on the last transmit byte. After writing the last transmit byte, the end of the transaction can
be detected by waiting for the last RDRNE interrupt or monitoring the TFST bit in the
ESPI Status Register.
The transmit underrun and receive overrun errors will not occur in an SPI mode Master. If
the RDRNE and TDRE requests have not been serviced before the current byte transfer
completes, SCLK will be paused until the Data Register is read and written. The transmit
underrun and receive overrun errors will occur in a Slave if the Slave’s software does not
keep up with the Master data rate. In this case the Shift Register in the Slave will be loaded
with all 1s.
In the SPI mode, the SCK is active only for the data transfer with one SCK period per bit
transferred. If the SPI bus has multiple Slaves, the Slave Select lines to all or all but one of
the Slaves must be controlled independently by software using GPIO pins. Figure 36 dis-
plays multiple character transfer in SPI mode.
Note: When character n is transferred via the Shift Register, software responds to the receive
request for character n-1 and the transmit request for character n+1.
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface