Z8F1680SH020SG Datasheet, PDF (255/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
230
transferred from the Slave to the Master. The transaction field labels are defined as
follows:
S Start
W Write
A Acknowledge
A Not Acknowledge
P Stop
17.2.5.4. Master Write Transaction with a 7-Bit Address
Figure 43 displays the data transfer format from a Master to a 7-bit addressed slave.
S
Slave
Address
W=0
A
Data
A
Data
A
Data
A/A P/S
Figure 43. Data Transfer Format—Master Write Transaction with a 7-Bit Address
Observe the following steps for a Master transmit operation to a 7-bit addressed slave:
1. The software initializes the MODE field in the I²C Mode Register for MASTER/
SLAVE Mode with either a 7-bit or 10-bit slave address. The MODE field selects the
address width for this mode when addressed as a slave (but not for the remote slave).
The software asserts the IEN bit in the I²C Control Register.
2. The software asserts the TXI bit of the I²C Control Register to enable transmit
interrupts.
3. The I²C interrupt asserts, because the I²C Data Register is empty.
4. The software responds to the TDRE bit by writing a 7-bit slave address plus the Write
bit (which is cleared to 0) to the I²C Data Register.
5. The software sets the start bit of the I²C Control Register.
6. The I²C controller sends a start condition to the I²C slave.
7. The I²C controller loads the I²C Shift Register with the contents of the I²C Data
Register.
8. After one bit of the address has been shifted out by the SDA signal, the transmit
interrupt asserts.
9. The software responds by writing the transmit data into the I²C Data Register.
10. The I²C controller shifts the remainder of the address and the Write bit out via the
SDA signal.
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller