Z8F1680SH020SG Datasheet, PDF (232/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
207
SCK (SSMD = 11,
PHASE = 0,
CLKPOL = 0)
SS
MOSI, MISO
Bit7
Bit0 Bit7
Bit0
Bit 7
frame n
frame n + 1
Figure 38. Synchronous Message Framing Mode (SSMD = 11), Multiple Frames
16.3.4. SPI Protocol Configuration
This section describes in detail how to configure the ESPI block for the SPI protocol. In
the SPI protocol the Master sources the SCK and asserts Slave Select signals to one or
more Slaves. The Slave Select signals are typically active Low.
16.3.4.1. SPI Master Operation
The ESPI block is configured for MASTER Mode operation by setting the MMEN bit = 1
in the ESPICTL register. The SSMD field of the ESPI Mode Register is set to 00 for SPI
protocol mode. The PHASE, CLKPOL and WOR bits in the ESPICTL register and the
NUMBITS field in the ESPI Mode Register must be set to be consistent with the Slave SPI
devices. Typically for an SPI Master, SSIO = 1 and SSPO = 0.
The appropriate GPIO pins are configured for the ESPI alternate function on the MOSI,
MISO and SCK pins. Typically the GPIO for the ESPI SS pin is configured in an alternate
function mode as well though the software can use any GPIO pin(s) to drive one or more
Slave select lines. If the ESPI SS signal is not used to drive a Slave select the SSIO bit
should still be set to 1 in a single Master system. Figures 39 and 40 display a block
diagram of the the ESPI configured as an SPI Master.
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface