Z8F1680SH020SG Datasheet, PDF (137/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
112
9.3.5. Timer 0–2 Control Registers
The Timer Control registers are described in Tables 63 through 65.
9.3.5.1. Timer 0–2 Control 0 Register
The Timer 0–2 Control 0 (TxCTL0) register together with TxCTL1 register determines
the timer operating mode. It also includes a programmable PWM deadband delay, two bits
to configure timer interrupt definition and a status bit to identify if the last timer interrupt
is due to an input capture event.
Table 63. Timer 0–2 Control 0 Register (TxCTL0)
Bit
7
Field TMODE[3]
Reset
0
R/W
R/W
Address
6
5
TICONFIG
0
0
R/W
R/W
4
3
CSC
0
0
R/W
R/W
F06H, F0EH, F16H
2
PWMD
0
R/W
1
0
INPCAP
0
0
R/W
R/W
Bit
[7]
TMODE[3]
[6:5]
TICONFIG
[4]
CSC
Description
Timer Mode High Bit
This bit, along with the TMODE[2:0] field in the TxCTL1 Register, determines the operating
mode of the timer. This bit is the most significant bit of the timer mode selection value. For
more details, see the description of the Timer 0–2 Control 1 Register (TxCTL1) on
page 113.
Timer Interrupt Configuration
This field configures timer interrupt definition.
0x = Timer Interrupt occurs on all defined Reload, Compare and Input Events.
10 = Timer Interrupt only on defined Input Capture/Deassertion Events.
11 = Timer Interrupt only on defined Reload/Compare Events.
Cascade Timers
0 = Timer Input signal comes from the pin.
1 = For Timer 0, Input signal is connected to Timer 2 output.
For Timer 1, Input signal is connected to Timer 0 output.
For Timer 2, Input signal is connected to Timer 1 output.
PS025015-1212
PRELIMINARY
Timers