Z8F1680SH020SG Datasheet, PDF (164/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
139
10.7.9. Multi-Channel Timer Channel-y High and Low Byte
Registers
Each channel has a 16-bit capture/compare register defined here as the Channel-y High
and Low Byte registers. When the timer is enabled, writes to these registers are buffered
and loading of the registers is delayed until the next timer end count, unless CHUE = 1.
Table 79. Multi-Channel Timer Channel-y High Byte Registers (MCTCHyH)*
Bit
7
6
5
4
3
2
1
0
Field
CHyH
Reset
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
See note.
Note: If 02H, 03H, 04H and 05H are in the Subaddress Register, they are accessible through Subregister 0.
Bit
7
6
5
4
3
2
1
0
Field
CHyL
Reset
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Note: If 02H, 03H, 04H and 05H are in the Subaddress Register, they are accessible through Subregister 1.
Bit
Description
[7:0]
CHyH,
CHyL
Multi-Channel Timer Channel-y High and Low Bytes
During a compare operation, these two bytes, {CHyH[7:0], CHyL[7:0]}, form a 16-bit value that
is compared to the current 16-bit timer count. When a match occurs, the Channel Output
changes state. The Channel Output value is set by the TPOL bit in the Channel-y Control
subregister. During a capture operation, the current Timer Count is recorded in these two bytes
when the appropriate Channel Input transition occurs.
Note: *y = A, B, C, D.
PS025015-1212
PRELIMINARY
Multi-Channel Timer