Z8F1680SH020SG Datasheet, PDF (16/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
xvi
Figure 27. Infrared Data Communication System Block Diagram . . . . . . . . . . . . . . 182
Figure 28. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 29. IrDA Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 30. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . 187
Figure 31. ADC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 32. ADC Convert Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 33. ESPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 34. ESPI Timing when PHASE=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 35. ESPI Timing when PHASE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 36. SPI Mode (SSMD = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 37. Synchronous Frame Sync Pulse mode (SSMD = 10) . . . . . . . . . . . . . . . . 206
Figure 38. Synchronous Message Framing Mode (SSMD = 11), Multiple Frames . . 207
Figure 39. ESPI Configured as an SPI Master in a Single Master, Single Slave 
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 40. ESPI Configured as an SPI Master in a Single Master, Multiple Slave 
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 41. ESPI Configured as an SPI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 42. I2C Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 43. Data Transfer Format—Master Write Transaction with a 7-Bit Address . 230
Figure 44. Data Transfer Format—Master Write Transaction with a 10-Bit Address 231
Figure 45. Data Transfer Format—Master Read Transaction with a 7-Bit Address . 233
Figure 46. Data Transfer Format—Master Read Transaction with a 10-Bit Address 234
Figure 47. Data Transfer Format—Slave Receive Transaction with 7-Bit Address . . 238
Figure 48. Data Transfer Format—Slave Receive Transaction with 10-Bit Address . 239
Figure 49. Data Transfer Format—Slave Transmit Transaction with 7-bit Address . 240
Figure 50. Data Transfer Format—Slave Transmit Transaction with 10-Bit Address 242
Figure 51. 8KB Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 52. 16KB Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 53. 24KB Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 54. Flowchart: Flash Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Figure 55. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
PS025015-1212
PRELIMINARY
List of Figures