Z8F1680SH020SG Datasheet, PDF (231/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
206
SCK (SSMD = 10,
PHASE = 0,
CLKPOL = 0,
SSPO = 1)
MOSI, MISO
Bit7 Bit6
Bit1 Bit0 Bit7 _{Bit 6}
SS
SSV
Figure 37. Synchronous Frame Sync Pulse mode (SSMD = 10)
16.3.3.3. Synchronous Framing with SS Mode
This mode is selected by setting the SSMD field of the Mode Register to 11. Figure 38
displays synchronous message framing mode with SS alternating between consecutive
frames. A frame consists of a fixed number of data bytes as defined by software. An
example of this mode is the Inter-IC Sound (I²S) protocol which is used to transfer left/
right channel audio data. The SSV indicates whether the corresponding bytes are left or
right channel data. The SSV value must be updated when servicing the TDRE interrupt/
request for the first byte in a left or write channel frame. This can be accomplished by
performing a word write when writing the first byte of the audio word, which will update
both the ESPI Data and Transmit Data Command words or by doing a byte write to update
SSV followed by a byte Write to the Data Register. The SS signal will lead the data by one
SCK period.
The transaction is terminated when the Master has no more data to transmit. After the last
bit is transferred, SCLK will stop and SS and SSV will return to their default states. A
transmit underrun error will occur at this point.
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface