Z8F1680SH020SG Datasheet, PDF (157/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
132
Table 72. Multi-Channel Timer Subaddress Register (MCTSA)
Bit
7
6
5
4
3
2
1
0
Field
MCTSA
Reset
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FA4H
Bit
Field
Reset
R/W
Address
10.7.5. Multi-Channel Timer Subregister x (0, 1, or 2)
The Multi-Channel Timer subregisters 0, 1 or 2 store the 8-bit data write to subregister or
8-bit data read from subregister. The Multi-Channel Timer Subaddress Register selects the
subregister to be written to or read from.
Table 73. Multi-Channel Timer Subregister x (MCTSRx)
7
6
5
4
3
2
1
0
MCTSRx
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FA5H, FA6H, FA7H
10.7.6. Multi-Channel Timer Control 0, Control 1 Registers
The Multi-Channel Timer Control registers (MCTCTL0, MCTCTL1) control Multi-
Channel Timer operation. Writes to the PRES field of the MCTCTL1 Register are
buffered when TEN = 1 and will not take effect until the next end of the cycle count
occurs.
Table 74. Multi-Channel Timer Control 0 Register (MCTCTL0)
Bit
7
6
5
4
3
2
Field
TCTST CHST TCIEN Reserved Reserved
Reset
0
0
0
0
0
0
R/W
R/W
R
R/W
R
R
R/W
Address
See note.
Note: If a 00H is in the Subaddress Register, it is accessible through Subregister 0.
1
TCLKS
0
R/W
0
0
R/W
PS025015-1212
PRELIMINARY
Multi-Channel Timer