Z8F1680SH020SG Datasheet, PDF (192/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
167
Bit
[5]
OE
[4]
FE
[3]
BRKD
[2]
TDRE
[1]
TXE
[0]
ATB
Description (Continued)
Receive Data and Autobaud Overrun Error
This bit is set just as in normal UART operation if a receive data overrun error occurs. This bit
is also set during LIN Slave autobaud if the BRG counter overflows before the end of the
autobaud sequence. This indicates that the receive activity is not an autobaud character or the
master baud rate is too slow. The ATB status bit will also be set in this case. This bit is cleared
by reading the Receive Data Register.
0 = No autobaud or data overrun error occurred.
1 = An autobaud or data overrun error occurred.
Framing Error
This bit indicates that a framing error (no stop bit following data reception) is detected. Reading
the Receive Data Register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
Break Detect
This bit is set in LIN mode if:
• It is in Lin Sleep state and a break of at least 4 bit times occurred (Wake-up event) or
• It is in Slave Wait Break state and a break of at least 11 bit times occurred (Break event) or
• It is in Slave Active state and a break of at least 10 bit times occurs. Reading the Status 0
Register or the Receive Data Register clears this bit.
0 = No LIN break occurred.
1 = LIN break occurred.
Transmitter Data Register Empty
This bit indicates that the Transmit Data Register is empty and ready for additional data.
Writing to the Transmit Data Register resets this bit.
0 = Do not write to the Transmit Data Register.
1 = The Transmit Data Register is ready to receive an additional byte for transmission.
Transmitter Empty
This bit indicates that the Transmit Shift Register is empty and character transmission is
completed.
0 = Data is currently transmitting.
1 = Transmission is complete.
LIN Slave Autobaud Complete
This bit is set in LIN SLAVE Mode when an autobaud character is received. If the ABIEN bit is
set in the LIN Control Register, then a receive interrupt is generated when this bit is set.
Reading the Status 0 Register clears this bit. This bit will be 0 in LIN MASTER Mode.
PS025015-1212
PRELIMINARY
LIN-UART