Z8F1680SH020SG Datasheet, PDF (225/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
200
16.2.4. Slave Select
The Slave Select signal is a bidirectional framing signal with several modes of operation
to support SPI and other synchronous serial interface protocols. The Slave Select mode is
selected by the SSMD field of the ESPI Mode Register. The direction of the SS signal is
controlled by the SSIO bit of the ESPI Mode Register. The SS signal is an input on slave
devices and is an output on the active Master device. Slave devices ignore transactions on
the bus unless their Slave Select input is asserted. In SPI MASTER Mode, additional
GPIO pins are required to provide Slave Selects if there is more than one slave device.
16.3. Operation
During a transfer, data is sent and received simultaneously by both the Master and Slave
devices. Separate signals are required for transmit data, receive data and the serial clock.
When a transfer occurs, a multi-bit (typically 8-bit) character is shifted out one data pin
and a multi-bit character is simultaneously shifted in on second data pin. An 8-bit shift
register in the Master and an 8-bit shift register in the Slave are connected as a circular
buffer. The ESPI Shift Register is buffered to support back-to-back character transfers in
high-performance applications.
A transaction is initiated when the Data Register is written in the Master device. The value
from the Data Register is transferred into the Shift Register and the SPI transaction begins.
At the end of each character transfer, if the next transmit value has been written to the Data
Register, the data and shift register values are swapped, which places the new transmit
data into the Shift Register and the Shift Register contents (receive data) into the Data
Register. At that point the Receive Data Register Not Empty signal is asserted (RDRNE
bit set in the Status Register). After software reads the receive data from the Data Register,
the Transmit Data Register Empty signal is asserted (TDRE bit set in the Status Register)
to request the next transmit byte. To support back-to-back transfers without an intervening
pause, the receive and transmit interrupts must be serviced when the current character is
being transferred.
The Master sources the Serial Clock (SCK) and Slave Select signal (SS) during the
transfer.
Internal data movement (by software) to/from the ESPI block is controlled by the
Transmit Data Register Empty (TDRE) and Receive Data Register Not Empty (RDRNE)
signals. These signals are read-only bits in the ESPI Status Register. When either the
TDRE or RDRNE bits assert, an interrupt is sent to the interrupt controller. In many cases
the software application is only moving information in one direction. In this case either the
TDRE or RDRNE interrupts can be disabled to minimize software overhead.
Unidirectional data transfer is supported by setting the ESPIEN1,0 bits in the Control
Register to 10 or 01.
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface