Z8F1680SH020SG Datasheet, PDF (104/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
79
Table 45. IRQ1 Enable Low Bit Register (IRQ1ENL)
Bits
Field
Reset
R/W
Address
7
6
5
4
3
2
1
PA7VENL PA6C0ENL PA5C1ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC5H
0
PA0ENL
0
R/W
Bit
Description
[7]
Port A Bit[7] or LVD Interrupt Request Enable Low Bit.
PA7VENL
[6]
Port A Bit[6] or Comparator 0 Interrupt Request Enable Low Bit.
PA6C0ENL
[5]
Port A Bit[5] or Comparator 1 Interrupt Request Enable Low Bit.
PA5C1ENL
[4:1]
Port A or Port D Bit[x] (x=1, 2, 3, 4) Interrupt Request Enable Low Bit.
PADxENL
[0]
PA0ENL
Port A Bit[0] Interrupt Request Enable Low Bit.
8.4.6. IRQ2 Enable High and Low Bit Registers
Table 46 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit
registers, shown in Tables 47 and 48 form a priority-encoded enabling for interrupts in the
Interrupt Request 2 Register. Priority is generated by setting bits in each register.
Table 46. IRQ2 Enable and Priority Encoding
IRQ2ENH[x] IRQ2ENL[x] Priority
0
0
Disabled
0
1
Level 1
1
0
Level 2
1
1
Level 3
Note: An x indicates the register bits from 0–7.
Description
Disabled
Low
Nominal
High
PS025015-1212
PRELIMINARY
Interrupt Controller