Z8F1680SH020SG Datasheet, PDF (220/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
195
14.3.7. ADC Clock Prescale Register
The ADC Clock Prescale Register, shown in Table 107, is used to provide a divided sys-
tem clock to the ADC. When this register is programmed with 0H, the System Clock is
used for the ADC Clock. DIV16 maintains the highest priority, DIV2 has the lowest prior-
ity.
Table 107. ADC Clock Prescale Register (ADCCP)
Bits
7
Field
Reset
R/W
Address
6
5
Reserved
0
4
3
DIV16
0
R/W
F76H
2
DIV8
0
1
DIV4
0
0
DIV2
0
Bit
[7:4]
[3]
DIV16
[2]
DIV8
[1]
DIV4
[0]
DIV2
Description
Reserved; must be 0.
Divide by 16
0 = Clock is not divided.
1 = System Clock is divided by 16 for ADC Clock.
Divide by 8
0 = Clock is not divided.
1 = System Clock is divided by 8 for ADC Clock.
Divide by 4
0 = Clock is not divided.
1 = System Clock is divided by 4 for ADC Clock.
Divide by 2
0 = Clock is not divided.
1 = System Clock is divided by 2 for ADC Clock.
Caution: The maximum ADC clock at 2.7V–3.6V is 5MHz. The maximum ADC clock at 1.8V–
2.7 V is 2.5 MHz. Set the Prescale Register correctly according to the different system
clocks. See the ADC Clock Prescale Register for details.
PS025015-1212
PRELIMINARY
Analog-to-Digital Converter