Z8F1680SH020SG Datasheet, PDF (335/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
310
Bit
Field
Reset
R/W
23.4.1. OCD Control Register
The OCD Control Register, shown in Table 164, controls the state of the On-Chip Debug-
ger. This register is used to enter or exit DEBUG mode and to enable the BRK instruction.
It can also reset the Z8 Encore! XP F1680 Series device.
A reset and stop function can be achieved by writing 81H to this register. A reset and go
function is achieved by writing 41H to this register. If the device is in DEBUG mode, a run
function is implemented by writing 40H to this register.
Table 164. OCD Control Register (OCDCTL)
7
DBGMOD
E
0
R/W
6
BRKEN
0
R/W
5
4
3
DBGACK BRKLOOP BRKPC
0
0
0
R/W
R/W
R/W
2
1
BRKZRO Reserved
0
0
R/W
R/W
0
RST
0
R/W
Bit
Description
[7]
DEBUG Mode
DBGMODE Setting this bit to 1 causes the device to enter DEBUG mode. When in DEBUG mode, the
eZ8 CPU stops fetching new instructions. Clearing this bit causes the eZ8 CPU to resume
execution. This bit is automatically set when a BRK instruction is decoded and breakpoints
are enabled.
0 = The device is running (operating in NORMAL Mode).
1 = The device is in DEBUG mode.
[6]
BRKEN
Breakpoint Enable
This bit controls the behavior of BRK instruction (op code 00H). By default, breakpoints are
disabled and the BRK instruction behaves like a NOP. If this bit is set to 1 and a BRK
instruction is decoded, the OCD takes action depending upon the BRKLOOP bit.
0 = BRK instruction is disabled.
1 = BRK instruction is enabled.
[5]
DBGACK
Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends a
Debug Acknowledge character (FFH) to the host when a breakpoint occurs. This bit
automatically clears itself when an acknowledge character is sent.
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
[4]
BRKLOOP
Breakpoint Loop
This bit determines what action the OCD takes when a BRK instruction is decoded and
breakpoints are enabled (BRKEN is 1). If this bit is 0, the DBGMODE bit is automatically set
to 1 and the OCD enters DEBUG mode. If BRKLOOP is set to 1, the eZ8 CPU loops on the
BRK instruction.
0 = BRK instruction sets DBGMODE to 1.
1 = eZ8 CPU loops on BRK instruction.
PS025015-1212
PRELIMINARY
On-Chip Debugger