Z8F1680SH020SG Datasheet, PDF (234/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
209
SS pin on the selected slave. Then, the active Master drives the clock and transmits data on
the SCK and MOSI pins to the SCK and MOSI pins on the Slave (including those Slaves
which are not enabled). The enabled slave drives data out its MISO pin to the MISO Mas-
ter pin.
When the ESPI is configured as a Master in a Multi-Master SPI system, the SS pin must
be configured as an input. The SS input signal on a device configured as a Master should
remain High. If the SS signal on the active Master goes Low (indicating another Master is
accessing this device as a Slave), a Collision error flag is set in the ESPI Status Register.
The Slave select outputs on a Master in a Multi-Master system must come from GPIO
pins.
16.3.4.3. SPI Slave Operation
The ESPI block is configured for SLAVE Mode operation by setting the MMEN bit = 0 in
the ESPICTL register and setting the SSIO bit = 0 in the ESPIMODE register. The SSMD
field of the ESPI Mode Register is set to 00 for SPI protocol mode. The PHASE, CLKPOL
and WOR bits in the ESPICTL register and the NUMBITS field in the ESPIMODE regis-
ter must be set to be consistent with the other SPI devices. Typically for an SPI Slave,
SSPO = 0.
If the Slave has data to send to the Master, the data must be written to the Data Register
before the transaction starts (first edge of SCK when SS is asserted). If the Data Register is
not written prior to the Slave transaction, the MISO pin outputs all 1s.
Due to the delay resulting from synchronization of the SS and SCK input signals to the
internal system clock, the maximum SCK baud rate that can be supported in SLAVE
Mode is the system clock frequency divided by 4. This rate is controlled by the SPI Mas-
ter. Figure 41 displays the ESPI configuration in SPI SLAVE Mode.
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface