Z8F1680SH020SG Datasheet, PDF (265/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
240
I2CISTAT Register is set to 1, thereby causing an interrupt. The RD bit is cleared to 0,
indicating a Write to the slave. The I²C controller acknowledges, indicating it is
available to accept the data.
4. The software responds to the interrupt by reading the I2CISTAT Register, which clears
the SAM bit. Because RD = 0, no immediate action is taken by the software until the
first byte of data is received. If the software is only able to accept a single byte, it sets
the NAK bit in the I2CCTL Register.
5. The Master detects the Acknowledge and sends the first byte of data.
6. The I²C controller receives the first byte and responds with Acknowledge or Not
Acknowledge, depending on the state of the NAK bit in the I2CCTL Register. The I²C
controller generates the receive data interrupt by setting the RDRF bit in the
I2CISTAT Register.
7. The software responds by reading the I2CISTAT Register, finding the RDRF bit = 1
and then reading the I2CDATA Register, which clears the RDRF bit. If the software
can accept only one more data byte, it sets the NAK bit in the I2CCTL Register.
8. The Master and Slave loops through Step 5 to Step 7 until the Master detects a Not
Acknowledge instruction or runs out of data to send.
9. The Master sends the stop or restart signal on the bus. Either of these signals can cause
the I²C controller to assert the stop interrupt (the stop bit = 1 in the I2CISTAT Regis-
ter). Because the slave received data from the master, the software takes no action in
response to the STOP interrupt other than reading the I2CISTAT Register to clear the
stop bit.
17.2.6.7. Slave Transmit Transaction With 7-bit Address
The data transfer format for a master reading data from a slave in 7-bit address mode is
displayed in Figure 49. The procedure that follows describes the I²C Master/Slave Con-
troller operating as a slave in 7-bit addressing mode and transmitting data to the bus mas-
ter.
S
Slave Address
R=1
A
Data
A
Data
A
P/S
Figure 49. Data Transfer Format—Slave Transmit Transaction with 7-bit Address
1. The software configures the controller for operation as a slave in 7-bit addressing
mode, as follows:
a. Initialize the MODE field in the I²C Mode Register for either SLAVE ONLY
mode or MASTER/SLAVE Mode with 7-bit addressing.
b. Optionally set the GCE bit.
c. Initialize the SLA[6:0] bits in the I²C Slave Address Register.
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller