Z8F1680SH020SG Datasheet, PDF (251/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
226
enabled when running in I²C FAST Mode (400 Kbps) and can also be used at lower data
rates.
17.2.2. I²C Interrupts
The I²C controller contains multiple interrupt sources that are combined into one interrupt
request signal to the interrupt controller. If the I²C controller is enabled, the source of the
interrupt is determined by which bits are set in the I2CISTAT Register. If the I²C control-
ler is disabled, the BRG controller is used to generate general-purpose timer interrupts.
Each interrupt source, other than the baud rate generator interrupt, features an associated
bit in the I2CISTAT Register that clears automatically when software reads the register or
performs another task, such as reading/writing the Data Register.
17.2.2.1. Transmit Interrupts
Transmit interrupts (TDRE bit = 1 in I2CISTAT) occur under the following conditions,
both of which must be true:
• The Transmit Data Register is empty and the TXI bit = 1 in the I²C Control Register.
• The I²C controller is enabled with one of the following elements:
– The first bit of a 10-bit address is shifted out.
– The first bit of the final byte of an address is shifted out and the RD bit is
deasserted.
– The first bit of a data byte is shifted out.
Writing to the I²C Data Register always clears the TRDE bit to 0.
17.2.2.2. Receive Interrupts
Receive interrupts (RDRF bit = 1 in I2CISTAT) occur when a byte of data has been
received by the I²C controller. The RDRF bit is cleared by reading from the I²C Data
Register. If the RDRF interrupt is not serviced prior to the completion of the next Receive
byte, the I²C controller holds SCL Low during the final data bit of the next byte until
RDRF is cleared, to prevent receive overruns. A receive interrupt does not occur when a
Slave receives an address byte or for data bytes following a slave address that do not
match. An exception is if the Interactive Receive Mode (IRM ) bit is set in the I2CMODE
Register, in which case Receive interrupts occur for all Receive address and data bytes in
SLAVE Mode.
17.2.2.3. Slave Address Match Interrupts
Slave address match interrupts (SAM bit = 1 in I2CISTAT) occur when the I²C controller
is in SLAVE Mode and an address received matches the unique slave address. The
General Call Address (0000_0000) and STARTBYTE (0000_0001) are recognized if the
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller