Z8F1680SH020SG Datasheet, PDF (267/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
242
S
Slave Address
1st Byte
W=0
A
Slave Address
2nd Byte
A
S
Slave Address
1st Byte
R=1
A
Data
A
Data
A
P
Figure 50. Data Transfer Format—Slave Transmit Transaction with 10-Bit Address
1. The software configures the controller for operation as a slave in 10-bit addressing
mode.
a. Initialize the MODE field in the I²C Mode Register for either SLAVE ONLY
mode or MASTER/SLAVE Mode with 10-bit addressing.
b. Optionally set the GCE bit.
c. Initialize the SLA[7:0] bits in the I2CSLVAD Register and SLA[9:8] in the I²C
MODE Register.
d. Set IEN = 1 and NAK = 0 in the I²C Control Register.
2. The Master initiates a transfer by sending the first address byte. The SLAVE Mode
I²C controller recognizes the start of a 10-bit address with a match to SLA[9:8] and
detects R/W bit = 0 (a Write from the master to the slave). The I²C controller
acknowledges indicating it is available to accept the transaction.
3. The Master sends the second address byte. The SLAVE Mode I²C controller compares
the second address byte with the value in SLA[7:0]. If there is a match, the SAM bit in
the I2CISTAT Register is set = 1, causing a slave address match interrupt. The RD bit
is set = 0, indicating a write to the slave. If a match occurs, the I²C controller acknowl-
edges on the I²C bus, indicating it is available to accept the data.
4. The software responds to the slave address match interrupt by reading the I2CISTAT
Register, which clears the SAM bit. Because the RD bit = 0, no further action is
required.
5. The Master sees the Acknowledge and sends a restart instruction, followed by the first
address byte with R/W set to 1. The SLAVE Mode I²C controller recognizes the
restart instruction followed by the first address byte with a match to SLA[9:8] and
detects R/W = 1 (the master reads from the slave). The slave I²C controller sets the
SAM bit in the I2CISTAT Register which causes the slave address match interrupt.
The RD bit is set = 1. The SLAVE Mode I²C controller acknowledges on the bus.
6. The software responds to the interrupt by reading the I2CISTAT Register clearing the
SAM bit. The software loads the initial data byte into the I2CDATA Register and sets
the TXI bit in the I2CCTL Register.
7. The Master starts the data transfer by asserting SCL Low. After the I²C controller has
data available to transmit, the SCL is released and the master proceeds to shift the first
data byte.
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller