Z8F1680SH020SG Datasheet, PDF (240/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
215
Bit
[1]
TEOF
[0]
SSV
Description
Transmit End of Frame
This bit is used in MASTER Mode to indicate that the data in the Transmit Data Register is the
last byte of the transfer or frame. When the last byte has been sent SS (and SSV) will change
state and TEOF will automatically clear.
0 = The data in the Transmit Data Register is not the last character in the message.
1 = The data in the Transmit Data Register is the last character in the message.
Slave Select Value
When SSIO = 1, writes to this register will control the value output on the SS pin. For more
details, see the SSMD field of the ESPI Mode Register on page 217.
16.4.3. ESPI Control Register
The ESPI Control Register, shown in Table 111, configures the ESPI for transmit and
receive operations.
Table 111. ESPI Control Register
Bits
Field
Reset
R/W
Address
7
DIRQE
0
R/W
6
ESPIEN1
0
R/W
5
BRGCTL
0
R/W
4
3
PHASE CLKPOL
0
0
R/W
R/W
F62H
2
WOR
0
R/W
1
MMEN
0
R/W
0
ESPIEN0
0
R/W
Bit
[7]
DIRQE
Description
Data Interrupt Request Enable
This bit is used to disable or enable data (TDRE and RDRNE) interrupts. Disabling the data
interrupts is needed to control data transfer by polling. Error interrupts are not disabled. To
block all ESPI interrupt sources, clear the ESPI interrupt enable bit in the Interrupt Controller.
0 = TDRE and RDRNE assertions do not cause an interrupt. Use this setting if controlling data
transfer by software polling of TDRE and RDRNE. The TUND, COL, ABT and ROVR bits
will cause an interrupt.
1 = TDRE and RDRNE assertions will cause an interrupt. TUND, COL, ABT and ROVR will
also cause interrupts. Use this setting when controlling data transfer via interrupt handlers.
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface