Z8F1680SH020SG Datasheet, PDF (100/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
75
8.4.3. Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) Register, shown in Table 39, stores interrupt requests for
both vectored and polled interrupts. When a request is presented to the interrupt controller,
the corresponding bit in the IRQ2 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 2 register to determine if any interrupt requests are pending.
Table 39. Interrupt Request 2 Register (IRQ2)
Bits
Field
Reset
R/W
Address
7
Reserved
0
R/W
6
MCTI
0
R/W
5
U1RXI
0
R/W
4
3
U1TXI
PC3I
0
0
R/W
R/W
FC6H
2
PC2I
0
R/W
1
PC1I
0
R/W
0
PC0I
0
R/W
Bit
[7]
[6]
MCTI
[5]
U1RXI
[4]
U1TXI
[3:0]
PCxI
Description
Reserved; must be 0.
Multi-channel timer Interrupt Request
0 = No interrupt request is pending for multi-channel timer.
1 = An interrupt request from multi-channel timer is awaiting service.
UART 1 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 1 receiver.
1 = An interrupt request from the UART 1 receiver is awaiting service.
UART 1 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 1 transmitter.
1 = An interrupt request from the UART 1 transmitter is awaiting service.
Port C Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service; x indicates the specific
GPIO Port C pin number (0–3).
PS025015-1212
PRELIMINARY
Interrupt Controller