Z8F1680SH020SG Datasheet, PDF (252/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
227
GCE bit = 1 in the I2CMODE Register. The software checks the RD bit in the I2CISTAT
Register to determine if the transaction is a Read or Write transaction. The General Call
Address and STARTBYTE address are also distinguished by the RD bit. The General Call
Address (GCA) bit of the I2CISTAT Register indicates whether the address match
occurred on the unique slave address or the General Call/STARTBYTE address. The SAM
bit clears automatically when the I2CISTAT Register is read.
If configured via the MODE[1:0] field of the I²C Mode Register for 7-bit slave
addressing, the most significant 7 bits of the first byte of the transaction are compared
against the SLA[6:0] bits of the Slave Address Register. If configured for 10-bit slave
addressing, the first byte of the transaction is compared against {11110,SLA[9:8], R/W}
and the second byte is compared against SLA[7:0].
17.2.2.4. Arbitration Lost Interrupts
Arbitration Lost interrupts (ARBLST bit = 1 in I2CISTAT) occur when the I²C controller
is in MASTER Mode and loses arbitration (outputs 1 on SDA and receives 0 on SDA).
The I²C controller switches to SLAVE Mode when this instance occurs. This bit clears
automatically when the I2CISTAT Register is read.
17.2.2.5. Stop/Restart Interrupts
A Stop/Restart event interrupt (SPRS bit = 1 in I2CISTAT) occurs when the I²C controller
is operating in SLAVE Mode and a stop or restart condition is received, indicating the end
of the transaction. The RSTR bit in the I²C State Register indicates whether the bit is set
due to a stop or restart condition. When a restart occurs, a new transaction by the same
master is expected to follow. This bit is cleared automatically when the I2CISTAT Regis-
ter is read. The Stop/Restart interrupt occurs only on a selected (address match) slave.
17.2.2.6. Not Acknowledge Interrupts
Not Acknowledge interrupts (NCKI bit = 1 in I2CISTAT) occur in MASTER Mode when
Not Acknowledge is received or sent by the I²C controller and the start or stop bit is not
set in the I²C Control Register. In MASTER Mode, the Not Acknowledge interrupt clears
by setting the start or stop bit. When this interrupt occurs in MASTER Mode, the I²C
controller waits until it is cleared before performing any action. In SLAVE Mode, the Not
Acknowledge interrupt occurs when a Not Acknowledge is received in response to data
sent. The NCKI bit clears in SLAVE Mode when software reads the I2CISTAT Register.
17.2.2.7. General Purpose Timer Interrupt from Baud Rate Generator
If the I²C controller is disabled (IEN bit in the I2CCTL Register = 0) and the BIRQ bit in
the I2CCTL Register = 1, an interrupt is generated when the baud rate generator (BRG)
counts down to 1. The baud rate generator reloads and continues counting, providing a
periodic interrupt. None of the bits in the I2CISTAT Register are set, allowing the BRG in
the I²C Controller to be used as a general-purpose timer when the I²C Controller is
disabled.
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller