Z8F1680SH020SG Datasheet, PDF (268/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
243
8. After the first bit of the first data byte has been transferred, the I²C controller sets the
TDRE bit which asserts the transmit data interrupt.
9. The software responds to the transmit data interrupt by loading the next data byte into
the I2CDATA Register.
10. The I²C Master shifts in the remainder of the data byte. The Master transmits the
Acknowledge (or Not Acknowledge, if this byte is the final data byte).
11. The bus cycles through Step 7 to Step 10 until the final byte is transferred. If the soft-
ware has not yet loaded the next data byte when the master brings SCL Low to trans-
fer the most significant data bit, the slave I²C controller holds SCL Low until the Data
Register is written.
When a Not Acknowledge is received by the slave, the I²C controller sets the NCKI
bit in the I2CISTAT Register, causing the NAK interrupt to be generated.
12. The software responds to the NAK interrupt by clearing the TXI bit in the I2CCTL
Register and by asserting the FLUSH bit of the I2CCTL Register.
13. When the Master has completed the Acknowledge cycle of the last transfer, it asserts a
stop or restart condition on the bus.
14. The Slave I²C controller asserts the stop/restart interrupt (sets the SPRS bit in the
I2CISTAT Register).
15. The software responds to the stop interrupt by reading the I2CISTAT Register and
clearing the SPRS bit.
17.3. I²C Control Register Definitions
This section defines the features of the following I²C Control registers.
I2C Data Register: see page 243
I2C Interrupt Status Register: see page 245
I2C Interrupt Status Register: see page 245
I2C Baud Rate High and Low Byte Registers: see page 248
I2C State Register: see page 250
I2C Mode Register: see page 253
I2C Slave Address Register: see page 255
17.3.1. I²C Data Register
The I²C Data Register listed in Table 119 contains the data that is to be loaded into the
Shift Register to transmit onto the I²C bus. This register also contains data that is loaded
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller