Z8F1680SH020SG Datasheet, PDF (218/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
193
14.3.5. Sample Settling Time Register
The Sample Settling Time Register, shown in Table 105, is used to program the length of
time from the SAMPLE/HOLD signal to the start signal, when the conversion can begin.
The number of clock cycles required for settling will vary from system to system
depending on the system clock period used. The system designer should program this
register to contain the number of clocks required to meet a 0.5 µs minimum settling time.
Table 105. Sample Settling Time (ADCSST)
Bits
7
6
5
4
3
2
1
0
Field
Reserved
SST
Reset
0
1
1
1
1
R/W
R
R/W
Address
F74H
Bit Position
[7:4]
[3:0]
SST
Value Description
(H)
0
Reserved; must be 0.
0–F Sample settling time in number of system clock periods to meet 0.5µs
minimum.
PS025015-1212
PRELIMINARY
Analog-to-Digital Converter