Z8F1680SH020SG Datasheet, PDF (101/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
76
8.4.4. IRQ0 Enable High and Low Bit Registers
Table 40 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit
registers, shown in Tables 41 and 42, form a priority-encoded enabling for interrupts in the
Interrupt Request 0 Register. Priority is generated by setting bits in each register.
Table 40. IRQ0 Enable and Priority Encoding
IRQ0ENH[x] IRQ0ENL[x] Priority
0
0
Disabled
0
1
Level 1
1
0
Level 2
1
1
Level 3
Note: x indicates the register bits from 0–7.
Description
Disabled
Low
Nominal
High
Bits
Field
Reset
R/W
Address
7
T2ENH
0
R/W
Table 41. IRQ0 Enable High Bit Register (IRQ0ENH)
6
T1ENH
0
R/W
5
T0ENH
0
R/W
4
3
U0RENH U0TENH
0
0
R/W
R/W
FC1H
2
I2CENH
0
R/W
1
SPIENH
0
R/W
0
ADCENH
0
R/W
Bit
Description
[7]
Timer 2 Interrupt Request Enable High Bit
T2ENH
[6]
Timer 1 Interrupt Request Enable High Bit
T1ENH
[5]
Timer 0 Interrupt Request Enable High Bit
T0ENH
[4]
UART 0 Receive Interrupt Request Enable High Bit
U0RENH
[3]
UART 0 Transmit Interrupt Request Enable High Bit
U0TENH
[2]
I²C Interrupt Request Enable High Bit
I2CENH
[1]
SPI Interrupt Request Enable High Bit
SPIENH
[0]
ADC Interrupt Request Enable High Bit
ADCENH
PS025015-1212
PRELIMINARY
Interrupt Controller