Z8F1680SH020SG Datasheet, PDF (236/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
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be configured with MMEN = 1, SSIO = 0 (SS is an input) and SS input = 0. A mode fault
sets the COL bit in the ESPI Status Register to 1. Writing a 1 to COL clears this error flag.
16.3.5.3. Receive Overrun
A receive overrun error occurs when a transfer completes and the RDRNE bit is still set
from the previous transfer. A receive overrun sets the ROVR bit in the ESPI Status Regis-
ter to 1. Writing a 1 to ROVR clears this error flag. The Receive Data Register is not over-
written and will contain the data from the transfer which initially set the RDRNE bit.
Subsequent received data is lost until the RDRNE bit is cleared.
In SPI MASTER Mode, a receive overrun will not occur. Instead, the SCK will be paused
until software responds to the previous RDRNE/TDRE requests.
16.3.5.4. SLAVE Mode Abort
In SLAVE Mode, if the SS pin deasserts before all bits in a character have been trans-
ferred, the transaction is aborted. When this condition occurs the ABT bit is set in the
ESPI Status Register. A Slave abort error resets the Slave control logic to idle state.
A Slave abort error is also asserted in SLAVE Mode, if BRGCTL = 1 and a baud rate
generator time-out occurs. When BRGCTL = 1 in SLAVE Mode, the baud rate generator
functions as a Watchdog Timer monitoring the SCK signal. The BRG counter is reloaded
every time a transition on SCK occurs while SS is asserted. The Baud Rate Reload
registers must be programmed with a value longer than the expected time between the SS
assertion and the first SCK edge, between SCK transitions while SS is asserted and
between the last SCK edge and SS deassertion. A time-out indicates the Master is stalled
or disabled. Writing a 1 to ABT clears this error flag.
16.3.6. ESPI Interrupts
ESPI has a single interrupt output which is asserted when any of the TDRE, TUND, COL,
ABT, ROVR or RDRNE bits are set in the ESPI Status Register. The interrupt is a pulse
which is generated when any one of the source bits initially sets. The TDRE and RDRNE
interrupts can be enabled/disabled via the Data Interrupt Request Enable (DIRQE) bit of
the ESPI Control Register.
A transmit interrupt is asserted by the TDRE status bit when the ESPI block is enabled and
the DIRQE bit is set. The TDRE bit in the Status register is cleared automatically when the
Data Register is written or the ESPI block is disabled. After the Data Register is loaded
into the Shift Register to start a new transfer, the TDRE bit will be set again, causing a
new transmit interrupt. In SLAVE Mode, if information is being received but not transmit-
ted the transmit interrupts can be eliminated by selecting Receive Only mode (ESPIEN1,0
= 01). A Master cannot operate in Receive Only mode since a write to the ESPI (Transmit)
Data Register is still required to initiate the transfer of a character even if information is
being received but not transmitted by the software application.
PS025015-1212
PRELIMINARY
Enhanced Serial Peripheral Interface