Z8F1680SH020SG Datasheet, PDF (254/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
229
17.2.5.1. Master Arbitration
If a Master loses arbitration during the address byte it releases the SDA line, switches to
SLAVE Mode and monitors the address to determine if it is selected as a Slave. If a Mas-
ter loses arbitration during the transmission of a data byte, it releases the SDA line and
waits for the next stop or start condition.
The Master detects a loss of arbitration when a 1 is transmitted but a 0 is received from the
bus in the same bit-time. This loss occurs if more than one Master is simultaneously
accessing the bus. Loss of arbitration occurs during the address phase (two or more
Masters accessing different slaves) or during the data phase, when the masters are
attempting to Write different data to the same Slave.
When a Master loses arbitration, the software is informed by means of the Arbitration Lost
interrupt. The software can repeat the same transaction at a later time.
A special case can occur when a Slave transaction starts just before the software attempts
to start a new master transaction by setting the start bit. In this case, the state machine
enters its Slave states before the start bit is set and as a result the I²C controller will not
arbitrate. If a Slave address match occurs and the I²C controller receives/transmits data,
the start bit is cleared and an Arbitration Lost interrupt is asserted. The software can
minimize the chance of this instance occurring by checking the busy bit in the I2CSTATE
Register before initiating a Master transaction. If a slave address match does not occur, the
Arbitration Lost interrupt will not occur and the start bit will not be cleared. The I²C
controller will initiate the master transaction after the I²C bus is no longer busy.
17.2.5.2. Master Address-Only Transactions
It is sometimes preferable to perform an address-only transaction to determine if a
particular slave device is able to respond. This transaction can be performed by
monitoring the ACKV bit in the I2CSTATE Register after the address has been written to
the I2CDATA Register and the start bit has been set. After the ACKV bit is set, the ACK
bit in the I2CSTATE Register determines if the slave is able to communicate. The stop bit
must be set in the I2CCTL Register to terminate the transaction without transferring data.
For a 10-bit slave address, if the first address byte is acknowledged, the second address
byte should also be sent to determine if the preferred Slave is responding.
Another approach is to set both the stop and start bits (for sending a 7-bit address). After
both bits have been cleared (7-bit address has been sent and transaction is complete), the
ACK bit can be read to determine if the Slave has acknowledged. For a 10-bit Slave, set
the stop bit after the second TDRE interrupt (which indicates that the second address byte
is being sent).
17.2.5.3. Master Transaction Diagrams
In the following transaction diagrams, the shaded regions indicate the data that is
transferred from the Master to the Slave and the unshaded regions indicate the data that is
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller