Z8F1680SH020SG Datasheet, PDF (53/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
28
Table 8. Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic Reset (Hex)¹ Page #
Multi-Channel Timer
FA0
MCT High Byte
FA1
MCT Low Byte
FA2
MCT Reload High Byte
FA3
MCT Reload Low Byte
FA4
MCT Subaddress
FA5
MCT Subregister 0
FA6
MCT Subregister 1
FA7
MCT Subregister 2
FA8–FBF
Reserved
MCTH
00
130
MCTL
00
130
MCTRH
FF
131
MCTRL
FF
131
MCTSA
XX
132
MCTSR0
XX
132
MCTSR1
XX
132
MCTSR2
XX
132
—
XX
Interrupt Controller
FC0
Interrupt Request 0
FC1
IRQ0 Enable High Bit
FC2
IRQ0 Enable Low Bit
FC3
Interrupt Request 1
FC4
IRQ1 Enable High Bit
FC5
IRQ1 Enable Low Bit
FC6
Interrupt Request 2
FC7
IRQ2 Enable High Bit
FC8
IRQ2 Enable Low Bit
FC9–FCC
Reserved
FCD
Interrupt Edge Select
FCE
Shared Interrupt Select
FCF
Interrupt Control
IRQ0
00
73
IRQ0ENH
00
76
IRQ0ENL
00
77
IRQ1
00
74
IRQ1ENH
00
78
IRQ1ENL
00
79
IRQ2
00
75
IRQ2ENH
00
80
IRQ2ENL
00
81
—
XX
IRQES
00
82
IRQSS
00
82
IRQCTL
00
83
GPIO Port A
FD0
Port A Address
PAADDR
00
58
FD1
Port A Control
PACTL
00
60
Notes:
1. XX=Undefined.
2. The Reserved space can be configured as General-Purpose Register File RAM depending on the user option bits
(see the User Option Bits chapter on page 277) and the on-chip PRAM size (see the Ordering Information chapter
on page 372). If the PRAM is programmed as General-Purpose Register File RAM on Reserved space, the start-
ing address always begins immediately after the end of General-Purpose Register File RAM.
PS025015-1212
PRELIMINARY
Register Map