Z8F1680SH020SG Datasheet, PDF (158/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
133
Bit
[7]
TCTST
[6]
CHST
[5]
TCIEN
[4:3]
2:0
TCLKS
Description
Timer Count Status
This bit indicates if a timer count cycle is complete and is cleared by writing 1 to the bit and is
cleared when TEN = 0.
0 = Timer count cycle is not complete.
1 = Timer count cycle is complete.
Channel Status
This bit indicates if a channel Capture/Compare event occurred. This bit is the logical OR of
the CHyEF bits in the MCTCHS1 register. This bit is cleared when TEN=0.
0 = No channel capture/compare event has occurred.
1 = A channel capture/compare event has occurred. One or more of the CHDEF, CHCEF,
CHBEF and CHAEF bits in the MCTCHS1 register are set.
Timer Count Interrupt Enable
This bit enables generation of timer count interrupt. A timer count interrupt is generated
whenever the timer completes a count cycle: counting up to Reload Register value or counting
down to zero depending on whether the TIMER mode is Count Modulo or Count up/down.
0 = Timer Count Interrupt is disabled.
1 = Timer Count Interrupt is enabled.
Reserved; must be 0.
Timer Clock Source
000 = System Clock (Prescaling enabled)
001 = Reserved
010 = System Clock gated by active High Timer Input signal (Prescaling enabled).
011 = System Clock gated by active Low Timer Input signal (Prescaling enabled).
100 = Timer I/O pin input rising edge (Prescaler disabled).
101 = Timer I/O pin input falling edge (Prescaler disabled).
110 = Reserved.
111 = Reserved.
Note: The input frequency of the Timer Input Signal must not exceed one-fourth the system
clock frequency.
PS025015-1212
PRELIMINARY
Multi-Channel Timer