Z8F1680SH020SG Datasheet, PDF (259/412 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F1680 Series
Product Specification
234
4. If this operation is a single-byte transfer, the software asserts the NAK bit of the I²C
Control Register so that after the first byte of data has been read by the I²C controller,
a Not Acknowledge instruction is sent to the I²C slave.
5. The I²C controller sends a start condition.
6. The I²C controller sends the address and Read bit out via the SDA signal.
7. The I²C slave acknowledges the address by pulling the SDA signal Low during the
next High period of SCL.
If the slave does not acknowledge the address byte, the I²C controller sets the NCKI
bit in the I²C Status Register, sets the ACKV bit and clears the ACK bit in the I²C
State Register. The software responds to the Not Acknowledge interrupt by setting the
stop bit and clearing the TXI bit. The I²C controller flushes the Transmit Data Regis-
ter, sends a stop condition on the bus and clears the stop and NCKI bits. The transac-
tion is complete and the following steps can be ignored.
8. The I²C controller shifts in the first byte of data from the I²C slave on the SDA signal.
9. The I²C controller asserts the receive interrupt.
10. The software responds by reading the I²C Data Register. If the next data byte is to be
the final byte, the software must set the NAK bit of the I²C Control Register.
11. The I²C controller sends a Not Acknowledge to the I²C slave if the next byte is the
final byte; otherwise, it sends an Acknowledge.
12. If there are more bytes to transfer, the I²C controller returns to Step 7.
13. A NAK interrupt (NCKI bit in I2CISTAT) is generated by the I²C controller.
14. The software responds by setting the stop bit of the I²C Control Register.
15. A stop condition is sent to the I²C slave.
17.2.5.7. Master Read Transaction with a 10-Bit Address
Figure 46 displays the read transaction format for a 10-bit addressed Slave.
S
Slave Address
1st Byte
W=0
A
Slave Address
2nd Byte
A
S
Slave Address
1st Byte
R=1
A
Data
A
Data
AP
Figure 46. Data Transfer Format—Master Read Transaction with a 10-Bit Address
The first 7 bits transmitted in the first byte are 11110XX. The two XX bits are the two
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
Observe the following data transfer procedure for a Read operation to a 10-bit addressed
slave:
PS025015-1212
PRELIMINARY
I2C Master/Slave Controller